Asynchronous vs. synchronous interfacing to time-triggered communication systems

Asynchronous vs. Synchronous Microporcessors

A circuit’s clock is often the single largest source of power dissipation is a digital system. Removing the clock should therefore reduce power consumption. The clock also forces the system to run at the worst case timing for every operation. Removing it should also allow the circuit to start the next operation upon completion of the current one. This is often the key motivation for designing a...

Synchronous Vs Asynchronous Design

Much of today’s logic design is based on two major assumptions: all signals are binary, and time is discrete. Both of these assumptions are made in order to simplify logic design. By assuming binary values on signals, simple Boolean logic can be used to describe and manipulate logic constructs. By assuming time is discrete, hazards and feedback can largely be ignored. However, as with many simp...

Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline

This paper describes a new technique for integrating asynchronous modules within a high-speed synchronous pipeline. Our design eliminates potential metastability problems by using a clock generated by a stoppable ring oscillator, which is capable of driving the large clock load found in present day microprocessors. Using the ATACS design tool, we designed highly optimized transistor-level circu...

SJOGREN AND MYERS : INTERFACING SYNCHRONOUS AND ASYNCHRONOUS MODULES 3 Controller

Asynchronous vs. Synchronous Design of RSA

Asynchronous designs have the potential to be robust with respect to changes in the physical environment. They also appear to consume less power and provide better performance compared to their synchronous counterparts. In this work, synchronous and asynchronous implementations of the modular multiplication that is the major part of the RSA algorithm is presented at the transistor level. Total ...